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Maxim Integrated Products 4
MAX11101
14-Bit, +5V, 200ksps ADC with 10A Shutdown
TIMING CHARACTERISTICS
(VAVDD = VDVDD = 4.75V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = 4.096V, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)
TIMING CHARACTERISTICS
(VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)
Note 2: VAVDD = VDVDD = +5V.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 4: Offset and reference errors nulled.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Defined as the change in positive full scale caused by a Q5% variation in the nominal supply voltage.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Acquisition Time
tACQ
1.1
F
s
SCLK to DOUT Valid
tDO
CDOUT = 50pF
50
ns
CS Fall to DOUT Enable
tDV
CDOUT = 50pF
80
ns
CS Rise to DOUT Disable
tTR
CDOUT = 50pF
80
ns
CS Pulse Width
tCSW
50
ns
CS Fall to SCLK Rise Setup
tCSS
100
ns
CS Rise to SCLK Rise Hold
tCSH
0
ns
SCLK High Pulse Width
tCH
65
ns
SCLK Low Pulse Width
tCL
65
ns
SCLK Period
tCP
208
ns
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Acquisition Time
tACQ
1.1
F
s
SCLK to DOUT Valid
tDO
CDOUT = 50pF
100
ns
CS Fall to DOUT Enable
tDV
CDOUT = 50pF
100
ns
CS Rise to DOUT Disable
tTR
CDOUT = 50pF
80
ns
CS Pulse Width
tCSW
50
ns
CS Fall to SCLK Rise Setup
tCSS
100
ns
CS Rise to SCLK Rise Hold
tCSH
0
ns
SCLK High Pulse Width
tCH
65
ns
SCLK Low Pulse Width
tCL
65
ns
SCLK Period
tCP
208
ns
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